`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/05/07 19:39:07
// Design Name: 
// Module Name: ad_ctrl
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module i2c_ctrl(

input                   clk_50m,
input                   rst_n,

output  reg [1:0]       cmd,
output  reg [7:0]       wr_data,
output  reg [15:0]      addr,
output      [6:0]       device_addr,

input                   done,
input       [7:0]       rd_data
);
    
assign  device_addr = 7'b0111_001;      //ADV7511

reg         [4:0]       wr_st;

always @ (posedge clk_50m)
if(!rst_n)
begin
    wr_st <= 0;
    cmd <= 0;
    addr <= 0;
    wr_data <= 0;
end
else
case(wr_st)
0:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h01; wr_data <= 8'h00;end
1:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h02; wr_data <= 8'h18;end
2:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h03; wr_data <= 8'h00;end
3:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h15; wr_data <= 8'h00;  end
4:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h16; wr_data <= 8'h61;  end
5:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h18; wr_data <= 8'h46;  end
6:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h40; wr_data <= 8'h80;  end
7:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h41; wr_data <= 8'h10;  end
8:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h48; wr_data <= 8'h48;  end
9:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h48; wr_data <= 8'ha8;  end
10:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h4c; wr_data <= 8'h06;  end
11:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h55; wr_data <= 8'h00;  end
12:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h55; wr_data <= 8'h08;  end
13:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h96; wr_data <= 8'h20;  end
14:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h98; wr_data <= 8'h03;  end
15:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h98; wr_data <= 8'h02;  end
16:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h9c; wr_data <= 8'h30;  end
17:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h9d; wr_data <= 8'h61;  end
18:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'ha2; wr_data <= 8'ha4;  end
19:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'h43; wr_data <= 8'ha4;  end
20:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'haf; wr_data <= 8'h16;  end
21:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'hde; wr_data <= 8'h9c;  end
22:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'he4; wr_data <= 8'h60;  end
23:
if( done ) begin cmd <= 2'b00; wr_st <= wr_st + 1'b1; end
else begin cmd <= 2'b01; addr <= 8'hfa; wr_data <= 8'h7d;  end
24: wr_st <= 24;

default : wr_st <= 0;
endcase
endmodule

// 01 00 ; Set N Value(6144)
// 02 18 ; Set N Value(6144)
// 03 00 ; Set N Value(6144)
// 15 00 ; Input 444 (RGB or YCrCb) with Separate Syncs
// 16 61 ; 44.1kHz fs, YPrPb 444
// 18 46 ; CSC disabled
// 40 80 ; General Control Packet Enable
// 41 10 ; Power Down control
// 48 48 ; Reverse bus, Data right justified
// 48 A8 ; Set Dither_mode - 12-to-10 bit
// 4C 06 ; 12 bit Output
// 55 00 ; Set RGB444 in AVinfo Frame
// 55 08 ; Set active format Aspect
// 96 20 ; HPD Interrupt clear
// 98 03 ; ADI required Write
// 98 02 ; ADI required Write
// 9C 30 ; ADI required Write
// 9D 61 ; Set clock divide
// A2 A4 ; ADI required Write
// 43 A4 ; ADI required Write
// AF 16 ; Set HDMI Mode
// BA 60 ; No clock delay
// DE 9C ; ADI required write
// E4 60 ; ADI required Write
// FA 7D ; Nbr of times to search for good phase